Title :
A MOS implementation of totally self-checking checker for the 1-out-of-3 code
Author :
Tao, D.L. ; Lala, Parag K. ; Hartmann, Carlos R P
Author_Institution :
Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA
fDate :
6/1/1988 12:00:00 AM
Abstract :
The problem of designing a totally self-checking (TSC) checker for the 1-out-of-3 code using combinational logic alone has not yet been solved. it is shown, however, that it is feasible to design such a checker in MOS technology. Analysis and simulation show that the proposed checker is a TSC checker for the 1-out-of-3 code with respect to a set of physical defects which occur frequently in MOS technology.<>
Keywords :
automatic testing; codes; combinatorial circuits; error detection; field effect integrated circuits; integrated logic circuits; logic testing; 1-out-of-3 code; 1/3 code; MOS implementation; NMOS; combinational logic; fault detection; fault tolerant systems; logic testing; totally self-checking checker; Analytical models; Built-in self-test; Circuit faults; Circuit simulation; Computer applications; Electrical fault detection; Fault detection; Fault tolerant systems; Logic design; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
