A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

Author

McIntyre, Hugh ; Wendell, Dennis ; Lin, K. James ; Kaushik, P. ; Seshadri, Suresh ; Wang, Alfred ; Sundararaman, V. ; Ping Wang ; Kim, Song ; Hsu, Wen-Jay ; Park, Hee-Choul ; Levinsky, Gideon ; Lu, Jiejun ; Chirania, M. ; Heald, Raymond ; Lazar, Paul ; Dh

Author_Institution

Sun Microsyst. Inc., Sunnyvale, CA, USA

Volume

40

Issue

1

fYear

2005

Firstpage

52

Lastpage

59

Abstract

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.

Keywords

CMOS memory circuits; SRAM chips; cache storage; integrated circuit design; memory architecture; microprocessor chips; reduced instruction set computing; 1.6 GHz; 4 Mbits; 64 bits; 8-metal-layer CMOS process; 90 nm; SPARC RISC microprocessor; SRAM arrays; array select signals; cache memories; clock information; global clock grid; global data repeaters; integrated circuit design; memory architectures; on-chip L2 data cache; random access memories; shift circuits; static sense amplifiers; CMOS process; Clocks; Flexible printed circuits; Microprocessors; Operational amplifiers; Random access memory; Reduced instruction set computing; Repeaters; Robustness; Timing; Cache memories; SPARC; integrated circuit design; manufacturability; memory architectures; microprocessors; random access memories; static sense amplifier;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2004.838017

Filename

1374990