Title :
A 130-nm triple-V/sub t/ 9-MB third-level on-die cache for the 1.7-GHz Itanium/spl reg/ 2 processor
Author :
Chang, J. ; Rusu, S. ; Shoemaker, J. ; Tam, S. ; Ming Huang ; Haque, M. ; Siufu Chiu ; Kevin Truong ; Karim, M. ; Leong, G. ; Desai, K. ; Goe, R. ; Kulkarni, S.
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Abstract :
The 18-way set-associative, single-ported 9 MB cache for the Itanium 2 processor uses 210 identical 48-kB sub-arrays with a 2.21-/spl mu/m/sup 2/ cell in a 130-nm 6-metal technology. The processor runs at 1.7 GHz at 1.35 V and dissipates 130 W. The 432-mm/sup 2/ die contains 592 M transistors, the largest transistor count reported for a microprocessor. This paper reviews circuit design and implementation details for the L3 cache data and tag arrays. The staged mode ECC scheme avoids a latency increase in the L3 tag. A high V/sub t/ implant improves the read stability and reduces the sub-threshold leakage.
Keywords :
cache storage; integrated circuit design; microprocessor chips; 1.35 V; 1.7 GHz; 130 W; 130 nm; 9 Mbits; ECC scheme; Itanium 2 processor; cache data; circuit design; clock distribution; computer architecture; microprocessor; on-die cache; power reduction; tag arrays; Circuit stability; Circuit synthesis; Clocks; Computer architecture; Decoding; Delay; Frequency; Implants; Microprocessors; Testing; Circuit design; clock distribution; computer architecture; manufacturability; microprocessor; on-die cache; power reduction; reliability; tag array; test;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.837970
