Title :
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems
Author :
Kennedy, Joseph ; Mooney, Randy ; Ellis, Robert ; Jaussi, James ; Borkar, Shekhar ; Choi, Jung-Hwan ; Kim, Chan-Kyong ; Kim, Woo-Seop ; Kim, Chang-Hyun ; Chang-Hyun Kim ; Cho, Soo-In ; Loeffler, Steffen ; Hoffmann, Jochen ; Hokenmaier, Wolfgang ; Houghton
Author_Institution :
Intel Labs., Hillsboro, OR, USA
Abstract :
We describe a DRAM interface operating at 3.6 Gb/s/pin implemented in 130-nm CMOS logic and 110-nm DRAM process technologies. It utilizes simultaneous bidirectional (SBD) signaling in a daisy-chained (repeated), point-to-point configuration to enable high performance scalable memory subsystems; and also provides direct attach capability for DRAMs to memory controllers or other logic devices. Source-synchronous strobes are used for data capture, minimizing strobe-to-data jitter. A low-jitter differential clock retimes the data at each DRAM on a per DIMM basis preventing jitter from accumulating in repeated data. The phase of this clock is adjusted on each DRAM to minimize the latency of the repeaters. 80 mW of total power is dissipated per DRAM I/O at 3.6 Gb/s. We present results from a system using both memory controller and DRAM repeater test chips.
Keywords :
CMOS memory circuits; DRAM chips; memory architecture; 110 nm; 130 nm; 3 Gbit/s; CMOS logic; DRAM process; DRAM repeater test chips; capacity-scalable memory subsystems; data capture; heterogeneous-voltage-capable DRAM interface; low-jitter differential clock; memory controllers; point-to-point configuration; simultaneous bidirectional signaling; source-synchronous strobes; strobe-to-data jitter; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Control systems; Delay; Jitter; Logic devices; Random access memory; Repeaters; CMOS; DRAM; Memory; capacity scalable; point-to-point; repeater; simultaneous bidirectional;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.837964
