A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture

Author

Choi, Sungdae ; Sohn, Kyomin ; Yoo, Hoi-Jun

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea

Volume

40

Issue

1

fYear

2005

Firstpage

254

Lastpage

260

Abstract

This paper presents a hybrid-type TCAM architecture which can utilize the benefits of both NOR and NAND-type TCAM cells: high speed and low power. A hidden bank selection scheme is proposed to activate limited amount of cells during the search operation avoiding additional timing penalty. Match fine repeaters and sub-match fine scheme are used for fast NAND search operation. A test chip with 144-kb TCAM capacity is implemented using 0.1-μm 1.2-V CMOS process to verify the proposed schemes. It shows 2.2 ns of match evaluation time on a 144-bit data search with 0.7 fJ/bit/search energy efficiency.

Keywords

CMOS memory circuits; NAND circuits; NOR circuits; content-addressable storage; logic design; low-power electronics; memory architecture; 0.1 micron; 1.2 V; 2.2 ns; hidden bank selection scheme; hybrid-type TCAM architecture; match line repeater; ternary content-addressable memory; timing penalty; CADCAM; CMOS process; Computer aided manufacturing; Energy efficiency; Helium; Repeaters; Testing; Timing; Transistors; Voltage; Content-addressable memory (CAM); hidden bank selection (HBS); high speed; hybrid type; low power; match line repeater (MLRPT);

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2004.837979

Filename

1375009