Abstract :
Through the advancement of integrated-circuit (IC) technology new approaches for programmable counting circuits are made feasible. Frequencies up to 1.2 GHz are programmable divided by a new breed of MSI-counters for ultra-high-frequency communications systems. After reviewing, the already known speed enhancing techniques, a new counting method (the patents of which is pending) is introduced to allow higher counting speeds. By using a shift register and some gates, applications at frequencies up to the gigahertz region, one to two orders of magnitude higher than conventional programmable counting, are made possible. The programmable counters developed use the new technique to eliminate the set-up time constraint of the IC employed. This boosts the counting frequency up to maximum toggle frequency of the IC. The method described is ideally suited for phase-locked loop (PLL) synthesizers for at least two reasons. First, it eliminates much of the prescaling required by slower counters. Second, it allows, in opposition to pulse-swallowing techniques, low-division ratios, and improved PLL performance. The simplicity of the method and the low package count make it suitable for MSI and LSI. This paper discusses the design approach used to implement programmable digital counters, for applications in nowadays fastest digital systems, utilizing currently available IC´s. With more and more versatility being offered by IC´s a fresh look is in order at conventional digital counter design. Decimal counter sections are available in IC-form usually with four stages to a package. Their use can afford considerable savings in space interconnections and power consumption.
