• DocumentCode
    1200084
  • Title

    Impact of low-impedance substrate on power supply integrity

  • Author

    Panda, Rajendran ; Sundareswaran, Savithri ; Blaauw, David

  • Author_Institution
    Motorola Inc., Austin, TX, USA
  • Volume
    20
  • Issue
    3
  • fYear
    2003
  • Firstpage
    16
  • Lastpage
    22
  • Abstract
    Although it is tempting to think of the power grid as an independent medium of the transfer of energy from the package to the devices in the IC, some second-order technology-related effects can sometimes cause unforeseen problems. This article focuses especially on the relationship of the power delivery system to the silicon substrate properties, and shows how a low-impendance substrate can make a substantial difference in the noise generated by the power grid.
  • Keywords
    VLSI; digital integrated circuits; integrated circuit design; power supply circuits; substrates; VLSI designs; capacitive coupling; delivery system power; digital integrated circuits; impact ionization; low-impedance substrate; power grid; power supply noise; resistive coupling; Acoustical engineering; Capacitance; Impact ionization; Packaging; Power grids; Power supplies; Rails; Semiconductor process modeling; Substrates; Voltage;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2003.1198681
  • Filename
    1198681
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1200084