• DocumentCode
    1200106
  • Title

    Clock and power gating with timing closure

  • Author

    Mukheijee, A. ; Marek-Sadowska, M.

  • Author_Institution
    Univ. of North Carolina, Charlotte, NC, USA
  • Volume
    20
  • Issue
    3
  • fYear
    2003
  • Firstpage
    32
  • Lastpage
    39
  • Abstract
    Assuming that delay is linearly dependent on local power supply voltage, the authors show how to set up an analysis to determine the effect of power supply variations on delay. This analysis can drive the introduction of clock gating, an increasingly popular technique for reducing dynamic power dissipation.
  • Keywords
    delays; integrated circuit design; low-power electronics; power supply circuits; timing circuits; clock gating; deep-submicron circuits; delay; dynamic power dissipation; local power supply voltage; power gating; power ground networks; power supply variations; timing closure; Circuits; Clocks; Current supplies; Delay effects; Frequency; Noise reduction; Power dissipation; Power supplies; Timing; Voltage;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2003.1198683
  • Filename
    1198683
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1200106