Title :
Microarchitectural dl/dt control
Author :
Grochowski, Ed ; Ayers, David ; Tiwari, Vivek
Author_Institution :
Univ. of California, Berkeley, CA, USA
Abstract :
This article takes a high level of the power-grid noise problem as it relates to the microarchitectural definition of an IC. Through a set of simulations, the authors relate the noise problem to the details of the circuit and clocking implementation giving insight into the possible method to reduce such noise.
Keywords :
circuit simulation; computer architecture; computer power supplies; microprocessor chips; performance evaluation; IC; IIR filter techniques; clocking; current simulator; high-level view; integrated circuits; microarchitectural dl/dt control; power distribution network; power-grid noise problem; voltage simulation; Clocks; Computational modeling; Integrated circuit noise; Microarchitecture; Microprocessors; Noise reduction; Packaging; Power systems; Regulators; Voltage;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2003.1198684
