Title :
Infrastructure IP for configuration and test of boards and systems
Author :
Clark, C.J. ; Ricchetti, Mike
Abstract :
Embedding infrastructure IP to optimize chip-level manufacturing test and debugging has recently become common practice. However, adopting the same approach for boards and systems requires a different family of infrastructure IP. This article introduces such a family and discusses how it can optimize manufacturing test and debugging, as well as support configurability, especially in today´s reconfigurable products.
Keywords :
field programmable gate arrays; integrated circuit testing; logic testing; printed circuits; chip-level manufacturing test; configurability; debugging; infrastructure IP; Automatic testing; Circuit testing; Costs; Debugging; Design engineering; Integrated circuit testing; Logic testing; Manufacturing; Semiconductor device testing; System testing;
Journal_Title :
Design & Test of Computers, IEEE
DOI :
10.1109/MDT.2003.1198689
