Analysis of true jitter arising from pulse-stuffing schemes

In synchronous digital hierarchy and plesiochronous digital hierarchy networks, it is frequently necessary to recover a data clock from a gapped clock derived from stuff information present at the desynchronizer. In this paper, a comprehensive analysis of the timing jitter resulting from phase-locked loop-type desynchronizers is presented. This analysis is different from the conventional analysis where the jitter is represented using a phase-error sequence. It is shown that such a simplified approach cannot accurately describe the jitter at the output of the desynchronizer. From the detailed analysis, it is also shown how the use of threshold modulation at the synchronizer reduces the low-frequency jitter at the desynchronizer. It has been demonstrated in the paper that when threshold modulation is used at the synchronizer, the dominating low-frequency jitter terms cannot be explained by the conventional jitter analysis methods. Therefore, in future networks, where tighter jitter performances are to be imposed on the synchronizers, jitter characterization using the proposed true jitter analysis technique would be very useful.