Title :
Performance improvement of tall triple gate devices with strained SiN layers
Author :
Collaert, N. ; De Keersgieter, A. ; Anil, K.G. ; Rooyackers, R. ; Eneman, G. ; Goodwin, M. ; Eyckens, B. ; Sleeckx, E. ; De Marneffe, J.F. ; De Meyer, K. ; Absil, P. ; Jurczak, M. ; Biesemans, S.
Author_Institution :
Interuniv. Microelectron. Center, Heverlee, Belgium
Abstract :
In this letter, we investigate the influence of tensile and compressive SiN layers on the device performance of triple-gate devices with 60-nm fin height and fin widths down to 35 nm. It will be shown that even for narrow fin devices, the nMOS performance improvement can be as high as 20% with tensile strained layers. The improvement seen for pMOS is lower, about 10%. Next to that both compressive as well as tensile SiN layers can increase the pMOS on-state current.
Keywords :
MOSFET; buried layers; electron mobility; silicon compounds; FinFET; SiN; SiN layers; fin height; fin width; mobility improvement; nMOS performance improvement; narrow fin devices; pMOS; tensile strained layers; triple gate device; Capacitive sensors; Compressive stress; Electron mobility; Etching; Fabrication; MOS devices; MOSFETs; Silicon compounds; Tensile stress; Thin film transistors; FinFET; mobility improvement; strain;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2005.857692
