Effect of low and high temperature anneal on process-induced damage of gate oxide

Author

King, Joseph C. ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

15

Issue

11

fYear

1994

Firstpage

475

Lastpage

476

Abstract

We have investigated the ability of high and low temperature anneals to repair the gate oxide damage due to simulated electrical stress caused by wafer charging resulting from plasma etching, etc. Even 800/spl deg/C anneal cannot restore the stability in interface trap generation. Even 900/spl deg/C anneal cannot repair the deteriorated charge-to-breakdown and oxide charge trapping. As a small consolation, the ineffectiveness of anneal in repairing the process-induced damage allows us to monitor the damages even at the end of the fabrication process.<>

Keywords

MOS integrated circuits; annealing; dielectric thin films; electric breakdown; integrated circuit reliability; integrated circuit technology; interface states; static electrification; 400 to 900 C; gate oxide damage repair; high temperature anneal; interface trap generation; low and high temperature anneal; process-induced damage; simulated electrical stress; wafer charging; Capacitors; Etching; Interface states; Plasma applications; Plasma immersion ion implantation; Plasma simulation; Plasma temperature; Simulated annealing; Stress; Voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.334672

Filename

334672