Title :
Interleaved parallel schemes
Author :
Seznec, Andre ; Lenfant, Jacques
Author_Institution :
IRISA, Rennes, France
fDate :
12/1/1994 12:00:00 AM
Abstract :
On vector supercomputers, vector register processors share a global highly interleaved memory. In order to optimize memory throughput, a single-instruction, multiple-data (SIMD) synchronization mode may be used on vector sections. We present an interleaved parallel scheme (IPS). Using IPS ensures an equitable distribution of elements on a highly interleaved memory for a wide range of vector strides. Access to memory may be organized in such a way that conflicts are avoided on memory and on the interconnection network
Keywords :
parallel machines; synchronisation; vector processor systems; global highly interleaved memory; interconnection network; interleaved parallel schemes; memory throughput; synchronization mode; vector register processors; vector supercomputers; Arithmetic; Computer networks; Concurrent computing; Intelligent networks; Manufacturing processes; Multiprocessor interconnection networks; Registers; Supercomputers; Throughput; Vector processors;
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on
