Title :
Diagnosing scan chain faults
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
Testing screens for good chips. However, when test fall out is high (low yield) it becomes necessary to diagnose faults so that the manufacturing process or physical design can be filed to improve yield. Several scan based diagnostic schemes are used in industry. They work when the scan chain itself is fault free. In this paper we describe a diagnosis system that can diagnose faults in a scan chain.<>
Keywords :
automatic testing; fault diagnosis; integrated circuit testing; logic testing; diagnosis system; pattern generation; scan based diagnostic schemes; scan chain faults; Automatic test pattern generation; Circuit faults; Clocks; Fault diagnosis; Latches; Manufacturing processes; Microscopy; Process design; Sequential circuits; Testing;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
