• DocumentCode
    1204025
  • Title

    Novel sorting network-based architectures for rank order filters

  • Author

    Chakrabarti, Chaitali ; Wang, Li-Yu

  • Author_Institution
    Telecommun. Res. Center, Arizona State Univ., Tempe, AZ, USA
  • Volume
    2
  • Issue
    4
  • fYear
    1994
  • Firstpage
    502
  • Lastpage
    507
  • Abstract
    This paper presents two novel sorting network-based architectures for computing high sample rate nonrecursive rank order filters. The proposed architectures consist of significantly fewer comparators than existing sorting network-based architectures that are based on bubble-sort and Batcher´s odd-even merge sort. The reduction in the number of comparators is obtained by sorting the columns of the window only once, and by merging the sorted columns in a way such that the number of candidate elements for the output is very small. The number of comparators per output is reduced even further by processing a block of outputs at a time. Block processing procedures that exploit the computational overlap between consecutive windows are developed for both the proposed networks.<>
  • Keywords
    CMOS digital integrated circuits; digital filters; pipeline processing; sorting; CMOS implementation; block processing procedures; comparators reduction; high sample rate nonrecursive filters; rank order filters; sorting network-based architectures; Computer architecture; Computer networks; Delay; Digital filters; Frequency; Information filtering; Information filters; Merging; Nonlinear filters; Sorting;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/92.335027
  • Filename
    335027