• DocumentCode
    1204103
  • Title

    Algorithm for modulo (2n+1) multiplication

  • Author

    Sousa, L.A.

  • Author_Institution
    Dept. of Electr. Eng., Inst. Superior Tecnico/INESC-ID, Lisboa, Portugal
  • Volume
    39
  • Issue
    9
  • fYear
    2003
  • fDate
    5/1/2003 12:00:00 AM
  • Firstpage
    752
  • Lastpage
    754
  • Abstract
    An algorithm for designing efficient modulo (2n+1) multipliers based on Booth recoding is proposed. With this algorithm, Wallace-tree adders can be used to design the fastest among all known modulo (2n+1) multipliers.
  • Keywords
    digital arithmetic; logic design; multiplying circuits; Booth recoding; Wallace-tree adders; modulo multiplication algorithm; modulo multiplier design; signal processing;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20030467
  • Filename
    1199986
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1204103