A 0.7-V 870- $\mu$ W Digital-Audio CMOS Sigma-Delta Modulator

This paper introduces a power-efficient, chopper-stabilized switched-capacitor sigma-delta (SigmaDelta) modulator that combines delayed input feedforward and single-comparator tracking multi-bit quantization to achieve high-precision, low-voltage analog-to-digital (A/D) conversion. An experimental prototype of the proposed architecture has been integrated in a 0.18-mum CMOS technology. The prototype operates from a 0.7-V supply voltage with a sampling rate of 5 MSamples/sec and consumes only 870 muW of total power. The converter achieves a dynamic range of 100 dB, a peak signal-to-noise ratio (SNR) of 100 dB and a peak signal-to-noise and distortion ratio (SNDR) of 95 dB for a 25-kHz signal bandwidth.