DocumentCode :
1204888
Title :
A Sub- 
s Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support
Author :
Kawasaki, Ken-Ichi ; Shiota, Tetsuyoshi ; Nakayama, Koichi ; Inoue, Atsuki
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki
Volume :
44
Issue :
4
fYear :
2009
fDate :
4/1/2009 12:00:00 AM
Firstpage :
1178
Lastpage :
1183
Abstract :
A sub-mus wake-up time power gating technique was developed for low-power SoCs. It uses two types of power switches and a separated power line bypassing rush current to suppress power-supply-voltage fluctuation. We applied this technique to a heterogeneous dual-core microprocessor fabricated in 90 nm CMOS technology. When wake-up time on the 2M-gate scale circuit was set to 0.24 mus , the supply voltage fluctuation was suppressed to 2.5 mV. The area overhead of this technique was less than 1% of the total die area.
Keywords :
CMOS integrated circuits; microprocessor chips; switches; system-on-chip; CMOS technology; heterogeneous dual-core microprocessor; low-power SoC; power line bypassing rush current; power switches; power-supply-voltage fluctuation suppression; time 0.24 mus; voltage 2.5 mV; wake-up time power gating technique; CMOS technology; Circuits; Data processing; Delay; Helium; Leakage current; Microprocessors; Personal digital assistants; Switches; Voltage fluctuations; Power gating; rush current; standby leakage; wake-up time;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2009.2014201
Filename :
4804973
Link To Document :
