DocumentCode
1204897
Title
A 0.7 V Single-Supply SRAM With 0.495 
m 
Cell in 65 nm Technology Utilizing Self-Write-B
Author
Kushida, Keiichi ; Suzuki, Azuma ; Fukano, Gou ; Kawasumi, Atsushi ; Hirabayashi, Osamu ; Takeyama, Yasuhisa ; Sasaki, Takahiko ; Katayama, Akira ; Fujimura, Yuki ; Yabe, Tomoaki
Author_Institution
Center for Semicond. Res. & Dev., Toshiba Corp., Kawasaki
Volume
44
Issue
4
fYear
2009
fDate
4/1/2009 12:00:00 AM
Firstpage
1192
Lastpage
1198
Abstract
We proposed a novel SRAM architecture with a high-density cell in low-supply-voltage operation. A self-write-back sense amplifier realizes cell failure rate improvement by more than two orders of magnitude at 0.6 V. A cascaded bit line scheme saves additional process cost for hierarchical bit line layer. A test chip with 256 kb SRAM utilizing 0.495 mum2 cell in 65 nm CMOS technology demonstrated 0.7 V single-supply operation.
Keywords
CMOS digital integrated circuits; SRAM chips; amplifiers; integrated circuit design; low-power electronics; nanoelectronics; CMOS technology; SRAM; cascaded bit line scheme; high-density cell; low-supply-voltage; memory size 256 KByte; self-write-back sense amplifier; single-supply operation; size 65 nm; voltage 0.6 V; voltage 0.7 V; CMOS technology; Costs; Logic circuits; Operational amplifiers; Parasitic capacitance; Power supplies; Random access memory; Stability; Testing; Voltage; Low-power design; SRAM; divided bit line; ultra-high-density cell;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.2009.2014009
Filename
4804974
Link To Document