DocumentCode :
1204948
Title :
Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking
Author :
Kurd, Nasser ; Mosalikanti, Praveen ; Neidengard, Mark ; Douglas, Jonathan ; Kumar, Rajesh
Author_Institution :
Intel Corp., Hillsboro, OR
Volume :
44
Issue :
4
fYear :
2009
fDate :
4/1/2009 12:00:00 AM
Firstpage :
1121
Lastpage :
1129
Abstract :
This paper describes the core and I/O clocking architecture of the next generation Intelreg Coretrade micro-architecture processor (Nehalem), designed on a 45 nm process technology. Local PLL placement provides modularity and power-efficient scalability by allowing independent frequency and voltage domains. Fast-locking, low-skew PLLs are used to achieve 56% lock time reduction and 30% long-tem jitter improvement. Adaptive frequency, supply, and duty cycle mechanisms combine for up to 5% core frequency gain at iso-voltage. Jitter attenuating DLLs with enhanced linearity and plusmn15% duty cycle correction drive a differential, low-swing I/O receiver clock distribution, reducing jitter by 25% and enabling 25.6 GB/s Intelreg QuickPath Interconnect bandwidth and three-channel DDR3 traffic up to 32 GB/s.
Keywords :
clocks; delay lock loops; jitter; microprocessor chips; phase locked loops; PLL placement; QuickPath Interconnect bandwidth; microarchitecture processor; next generation Intel Core; phase lock loops placement; Bandwidth; Clocks; Drives; Frequency; Jitter; Linearity; Phase locked loops; Process design; Scalability; Voltage; IA; Intel¯ QuickPath; delay-locked loop (DLL); interconnect; memory controller; phase-locked loop (PLL);
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2009.2014023
Filename :
4804981
Link To Document :
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