A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS

Author

Klim, Peter J. ; Barth, John ; Reohr, William R. ; Dick, David ; Fredeman, Gregory ; Koch, Gary ; Le, Hien M. ; Khargonekar, Aditya ; Wilcox, Pamela ; Golz, John ; Kuang, Jente B. ; Mathews, Abraham ; Law, Jethro C. ; Luong, Trong ; Ngo, Hung C. ; Freese,

Author_Institution

Syst. & Technol. Group, IBM, Austin, TX

Volume

44

Issue

4

fYear

2009

fDate

4/1/2009 12:00:00 AM

Firstpage

1216

Lastpage

1226

Abstract

We describe a single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on-chip word-line voltage supply generation , a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair control, on-chip OTPROM programming voltage generation, clock generation and distribution, array built-in self-test circuitry (ABIST), user logic and pervasive logic. The eDRAM employs a programmable pipeline, achieving 1.8 ns latency, and features concurrent refresh capability.

Keywords

CMOS memory circuits; DRAM chips; built-in self test; cache storage; silicon-on-insulator; SOI CMOS; array built-in self-test circuitry; cache subsystem prototype; clock generation; embedded DRAM; frequency 2 GHz; onchip word-line voltage supply generation; one-time-programmable read-only memory; pervasive logic; programmable pipeline; user logic; Built-in self-test; Clocks; Logic arrays; Logic circuits; Logic programming; Pipelines; Programmable logic arrays; Prototypes; Random access memory; Voltage control; 45 nm; Cache; SOI; embedded DRAM;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2009.2014207

Filename

4804985