DocumentCode :
1205085
Title :
On the performance limit for Si MOSFET´s: experimental study
Author :
Toriumi, Akira ; Iwase, Masao ; Yoshimi, Makoto
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Volume :
35
Issue :
7
fYear :
1988
fDate :
7/1/1988 12:00:00 AM
Firstpage :
999
Lastpage :
1003
Abstract :
Short-channel MOSFETs fabricated by direct-write electron-beam lithography have been examined with regard to parameters such as channel length, oxide thickness, and substrate doping concentration. A simple relationship between channel length and transconductance in the saturated region has been derived from the experimental results, and the performance of MOSFETs with zero channel lengths has been evaluated as a function of oxide thickness. The ultimate performance of MOSFETs with both zero channel length and zero oxide thickness has been estimated to be about 3000 mS/mm. This limitation is attributed to the saturation velocity and the finite inversion layer thickness. The electron saturation velocity in the inversion layer has been confirmed experimentally to be 1.0×107 cm/s
Keywords :
VLSI; elemental semiconductors; field effect integrated circuits; insulated gate field effect transistors; silicon; 3000 mS; MOS VLSI; MOSFETs; Si; channel length; direct-write electron-beam lithography; electron saturation velocity; elemental semiconductor; finite inversion layer thickness; oxide thickness; performance limit; saturated region; short channel devices; substrate doping concentration; transconductance; zero channel lengths; Circuit synthesis; Electrons; Gallium arsenide; Lithography; MOSFET circuits; Performance evaluation; Semiconductor devices; Substrates; Transconductance; Very large scale integration;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/16.3357
Filename :
3357
Link To Document :
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