Simulation of MOSFET lifetime under AC hot-electron stress

Author

Kuo, Mary M. ; Seki, Koichi ; Lee, Peter M. ; Choi, J.Y. ; Ko, Ping K. ; Hu, Chenming

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Volume

35

Issue

7

fYear

1988

fDate

7/1/1988 12:00:00 AM

Firstpage

1004

Lastpage

1011

Abstract

A substrate current model and a quasistatic hot-electron-induced MOSFET degradation model have been implemented using the Substrate Current And Lifetime Evaluator (SCALE) package. It is shown that quasistatic simulation is valid for a class of waveforms that includes those encountered in inverter-based logic circuits. The validity and limitations of the model are illustrated with experimental results. SCALE is linked to SPICE externally in a pre- and postprocessor fashion to form an independent simulator. The preprocessor interprets the input deck and requests SPICE to output the transient node voltages of the user-selected devices. The postprocessor then calculates the transient substrate current and makes a lifetime prediction

Keywords

circuit reliability; electronic engineering computing; hot carriers; insulated gate field effect transistors; semiconductor device models; AC hot-electron stress; MOSFET lifetime; SCALE package; SPICE; Substrate Current And Lifetime Evaluator; hot electron induced degradation model; inverter-based logic circuits; lifetime prediction; postprocessor; preprocessor; quasistatic simulation; reliability; substrate current model; transient node voltages; transient substrate current; user-selected devices; Circuit simulation; Computational modeling; Degradation; Laboratories; Logic circuits; MOSFET circuits; Monitoring; SPICE; Stress; Very large scale integration;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.3358

Filename

3358