Title :
Synchro-tokens: a deterministic GALS methodology for chip-level debug and test
Author :
Heath, Matthew W. ; Burleson, Wayne P. ; Harris, Ian G.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
This paper describes a novel deterministic globally-asynchronous locally-synchronous (GALS) methodology called "synchro-tokens". Wrappers around the synchronous blocks keep the system globally asynchronous while ensuring that each transition, although arriving at a nondeterministic time, is sensed by the synchronous block during a deterministic cycle of the local clock. This determinism facilitates debug and test methodologies, such as the use of stored-pattern testers, which are effective only when the system behavior is predictable and repeatable. Applications of synchro-tokens to GALS systems with two or more synchronous blocks and one or more asynchronous data channels are shown. Synchro-tokens supports both pipelined and unpipelined channels and a variety of clock generation methodologies. Novel schematic level designs of the wrapper components in a 180-nm technology are used to compare the performance of several different deterministic GALS design styles.
Keywords :
asynchronous circuits; clocks; integrated circuit testing; logic testing; system-on-chip; GALS systems; SoC; asynchronous data channels; chip-level debug; clock generation; deterministic globally-asynchronous locally-synchronous methodology; pipelined channels; stored-pattern testers; synchro-tokens; system behavior; unpipelined channels; wrapper components; Clocks; Design methodology; Frequency; Logic circuits; Logic design; Performance loss; System performance; System testing; System-on-a-chip; Token networks; Index Terms- GALS; SoC.; debug; globally asynchronous locally synchronous; nondeterminism; test;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.2005.203
