Two-dimensional numerical analysis of the floating region in SOI MOSFETs

Author

Edwards, Susan P. ; YALLUP, Kevin J. ; De Meyer, Kristin M.

Author_Institution

IMEC, Heverlee, Belgium

Volume

35

Issue

7

fYear

1988

fDate

7/1/1988 12:00:00 AM

Firstpage

1012

Lastpage

1020

Abstract

Results of simulating SOI/MOSFET (silicon-on-insulator/metal-oxide-semiconductor field-effect-transistor) devices using the full two-dimensional numerical solution of the classical semiconductor equations are presented. Particular attention has been paid to the role of the floating region, and it is demonstrated that removal of this phenomenon is important for the improvement of the performance of SOI/MOSFET devices. Several methods, such as applying a back gate bias or using thinner (100-nm) films, are investigated as a means of controlling this undesirable feature. It is shown that the use of thin films has major advantages. It is concluded from a study of the effect of lifetime on device performance that improved film quality can have an adverse effect on the I_d-V_d characteristics, giving an enhanced kink and earlier breakdown on 0.3-μm silicon films

Keywords

field effect integrated circuits; insulated gate field effect transistors; semiconductor device models; 100 to 300 nm; SOI MOSFETs; Si; back gate bias; classical semiconductor equations; device performance; floating region; lifetime; thin films; two-dimensional numerical solution; Degradation; Equations; Impact ionization; MOSFETs; Numerical analysis; Radiative recombination; Semiconductor device modeling; Semiconductor films; Semiconductor process modeling; Silicon;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.3359

Filename

3359