• DocumentCode
    1205728
  • Title

    Aliasing probability calculations for arbitrary compaction under independently selected random test vectors

  • Author

    Hadjicostis, Christoforos N.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Illinois Univ., Champaign, IL, USA
  • Volume
    54
  • Issue
    12
  • fYear
    2005
  • Firstpage
    1614
  • Lastpage
    1627
  • Abstract
    This paper discusses a systematic methodology for calculating the exact aliasing probability associated with schemes that use an arbitrary finite-state machine to compact the response of a combinational circuit to a sequence of independently selected, random test input vectors. The proposed approach identifies the strong influence of fault activation probabilities on the probability of aliasing and uses an asymmetric error model to simultaneously track the states of two (fictitious) compactors, one driven by the response of the fault-free combinational circuit and one driven by the response of the faulty combinational circuit. By deriving the overall Markov chain that describes the combined behavior of these two compactors, we are able to calculate the exact aliasing probability for any test sequence length. In particular, for long enough sequences, the probability of aliasing is shown to only depend on the stationary distribution of the Markov chain. The insights provided by our analysis are used to evaluate the testing performance of simple examples of nonlinear compactors and to demonstrate regimes where they exhibit lower aliasing probability than linear compactors with the same number of states. Finally, by establishing connections with previous work that evaluated aliasing probability in linear compactors, our analysis clarifies the role played by the entropy of the stationary distribution of the compactor states.
  • Keywords
    Markov processes; combinational circuits; finite state machines; logic testing; random processes; statistical distributions; Markov chain; aliasing probability calculation; arbitrary finite-state machine compaction; asymmetric error model; combinational circuit; fault activation probabilities; independently selected random test vectors; nonlinear compactors; stationary distribution; test sequence length; Circuit faults; Circuit testing; Combinational circuits; Compaction; Entropy; Fault diagnosis; Fault location; Performance analysis; Probability; System testing; Index Terms- Aliasing probability; compaction; fault activation probabilities; random testing.;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/TC.2005.189
  • Filename
    1524941