Digital tanlock loop without a phase shifter

This paper presents an improved digital tanlock loop architecture that has linear phase detector characteristics. These characteristics were linearized by removing the fixed time delay unit in the original time delay tanlock loop (TDTL) and using a modified DCO (digital controlled oscillator). The modified DCO incorporates lookup tables to generate two outputs with quadrature relationship. The two outputs control the circuit blocks used to sample the loop input signal. The performance of the proposed system was evaluated using various input signals to assess its acquisition speed. The simulation results using Simulink/MATLAB indicate an improvement in the acquisition performance of the proposed system compared to the original TDTL. In addition, the implementation complexity of the proposed system is also improved as the realization of two DCO outputs lends itself to FPGA implementation which may be readily achieved using only one direct digital synthesizer (DDS) with two lookup tables to stores both values of sine and cosine waveforms which are used for the sampling of the input signal.