A novel PLL lock and out-of-lock detect scheme based on a feedback sampling of PLL

The existing state of the art lock/out-of-lock detection schemes used in PLL (Phase lock loop) suffers from process, voltage and temperature (PVT) variations and has limited accuracy especially in fractional PLL mode of operation. Moreover, the schemes are not suitable to detect both lock and out-of-lock condition accurately. This paper describes a novel mixed signal scheme which incorporates detection of both lock and out-of-lock conditions of a PLL. The scheme covers integer and fractional PLL modes of operations and programmable to generate lock condition to a very high accuracy. Furthermore, this digital detection scheme is not prone to process, voltage and temperature variations.