DocumentCode
1206916
Title
A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell
Author
Yu-Che Yang ; Shih-An Yu ; Tao Wang ; Shey-Shi Lu
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
15
Issue
11
fYear
2005
Firstpage
754
Lastpage
756
Abstract
A divide-by-1/1.5 divider cell using a dual edge-trigger technique is proposed. Based on this divider cell, a dual-mode programmable divide-by-X circuit is demonstrated in 0.18-μm CMOS technology, where X=P or P.5 in one mode and 2P or 2P+1 in the other mode with P=128-255. When operated in the divide-by-2P/2P+1 mode, this circuit outputs a signal with 50% duty cycle. Theoretically, P can be any arbitrary and programmable integer.
Keywords
CMOS logic circuits; dividing circuits; phase locked loops; programmable circuits; 0.18 micron; CMOS technology; divider cell; dual edge-trigger technique; dual-mode programmable divide-by-X circuit; fractional divider; phase-locked loop; programmable divider; 1f noise; CMOS technology; Circuits; Latches; Multiplexing; Phase locked loops; Phase modulation; Phase noise; Quantization; Signal to noise ratio; 50% duty cycle and phase-locked loop (PLL); fractional divider; programmable divider;
fLanguage
English
Journal_Title
Microwave and Wireless Components Letters, IEEE
Publisher
ieee
ISSN
1531-1309
Type
jour
DOI
10.1109/LMWC.2005.858978
Filename
1525064
Link To Document