A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass ΣΔ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed ΣΔ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass ΣΔ modulators with switched-capacitor architectures. The second-order ΣΔ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-μm BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.