Title :
A 1.0-V VDD CMOS active-pixel sensor with complementary pixel architecture and pulsewidth modulation fabricated with a 0.25-μm CMOS process
Author :
Xu, Chen ; Zhang, WeiQuan ; Ki, Wing-Hung ; Chan, Mansun
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China
fDate :
12/1/2002 12:00:00 AM
Abstract :
In this paper, an architecture to design a CMOS active-pixel sensor (APS) in an extremely low-voltage environment imposed by advanced CMOS technology is proposed. A complementary active pixel sensor (CAPS) architecture is developed to allow a CMOS active pixel to operate at a voltage below 1 V VDD without using bootstrapping techniques. A fixed voltage deference (FVD) method with correlated double sampling is used to increase the dynamic range of the readout circuit. Both the CAPS and FVD readout circuits together, with an 8-b analog-to-digital converter, are implemented in a commercially available 0.25-μm, single-poly and five-metal CMOS process. Measurement results show that the circuit is functional at a VDD below 1 V with 15-dB added dynamic range compared with a conventional CMOS APS architecture.
Keywords :
CMOS image sensors; analogue-digital conversion; low-power electronics; pulse width modulation; readout electronics; 0.25 micron; 0.25-μm CMOS process; 1.0 V; CMOS active-pixel sensor; analog-to-digital converter; complementary active pixel sensor architecture; complementary pixel architecture; correlated double sampling; extremely low-voltage environment; fixed voltage deference method; pulsewidth modulation; readout circuit dynamic range; single-poly five-metal CMOS process; CMOS image sensors; CMOS process; CMOS technology; Circuits; Dynamic range; Dynamic voltage scaling; Pulse modulation; Signal to noise ratio; Space vector pulse width modulation; Threshold voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2002.804346
