DocumentCode
1208017
Title
Determining the drain doping in DMOS transistors using the hump in the leakage current
Author
Zupac, Dragan ; Anderson, Steven R. ; Schrimpf, Ronald D. ; Galloway, Kenneth F.
Author_Institution
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ, USA
Volume
41
Issue
12
fYear
1994
fDate
12/1/1994 12:00:00 AM
Firstpage
2326
Lastpage
2336
Abstract
The hump in the leakage current of double-diffused metal-oxide-semiconductor (DMOS) transistors observed for low drain voltages is explained. This hump is due to surface generation current of the gate-controlled diode formed by the base-drain p-n junction. The drain bias of the DMOS transistor is shown to have the same effect on the charge at the drain surface as the body bias in the conventional MOSFET. The body effect is used to develop a new method for determining the drain doping in DMOS transistors. This method is nondestructive, and does not require special test structures. Instead, electrical measurements are performed on conventional DMOS transistors. The method is ideally suited for determining the doping in the drain region of interest. Specifically, in DMOS transistors in which a surface implant is used to reduce the on-resistance, the method provides the doping concentration in the implanted region. In DMOS transistors which do not have the surface implant, the method yields the doping concentration in the drain epitaxial layer. In this study, the method is illustrated by determining the drain doping for six discrete power MOSFET device types from three different manufacturers
Keywords
doping profiles; leakage currents; power MOSFET; semiconductor device models; semiconductor doping; DMOS transistors; base-drain p-n junction; body effect; doping concentration; double-diffused metal-oxide-semiconductor transistors; drain doping; drain epitaxial layer; drain voltages; electrical measurements; gate-controlled diode; leakage current; power MOSFET device types; surface generation current; surface implant; Diodes; Doping; Electric variables measurement; Implants; Leakage current; Low voltage; MOSFET circuits; Nondestructive testing; P-n junctions; Performance evaluation;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.337445
Filename
337445
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