Title :
A new technique for measuring coupling coefficients and 3-D capacitance characterization of floating-gate devices
Author :
Choi, Woong L. ; Kim, Dae M.
Author_Institution :
Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol., South Korea
fDate :
12/1/1994 12:00:00 AM
Abstract :
The characteristics of the capacitance in floating-gate devices are comprehensively investigated. The capacitive coupling coefficient (αc) between the control and floating gates is measured simultaneously, by a new technique, with the shift in threshold voltage during the programming. The present results are compared with those found from other methods and the dependence of αc on applied voltages is examined. It is also shown that the αc -data from a set of test patterns with varying floating-gate widths leads to the 3-D characterization of small geometry floating gate devices down to subfemto Farads. These measured characteristics are discussed in correlation with the effects of both the short channel length and of the narrow gate width
Keywords :
EPROM; MOS memory circuits; capacitance measurement; integrated circuit measurement; integrated circuit testing; 3D capacitance characterization; EEPROMs; MOS devices; capacitive coupling coefficient; floating-gate devices; narrow gate width; short channel length; small geometry devices; test patterns; threshold voltage; Capacitance measurement; Capacitance-voltage characteristics; Data mining; Geometry; Nonvolatile memory; Substrates; Testing; Threshold voltage; Virtual colonoscopy; Voltage control;
Journal_Title :
Electron Devices, IEEE Transactions on