Title :
On single-electron technology full adders
Author :
Sulieman, Mawahib H. ; Beiu, Valeriu
Author_Institution :
Coll. of Eng., United Arab Emirates Univ., Al-Ain, United Arab Emirates
Abstract :
This paper reviews several full adder (FA) designs in single-electron technology (SET). In addition to the structure and size (i.e., number of devices), this paper tries to provide a quantitative and qualitative comparison in terms of delay, sensitivity to (process) variations, and complexity of the design. This will allow for a better understanding of the advantages and disadvantages of each solution. An optimization of an SET FA (combining one of the SET FAs with a static buffer), together with a new SET FA design (based on capacitive SET threshold logic gates), will also be described and compared with the other SET FAs.
Keywords :
CMOS logic circuits; adders; logic design; logic gates; single electron transistors; threshold logic; SET FA design; capacitive SET threshold logic gates; complexity design; full adder designs; process variations; sensitivity; sensitivity-variations; single-electron technology; static buffer; Adders; Birth disorders; CMOS logic circuits; CMOS technology; Capacitors; Circuit simulation; Delay; Energy consumption; Logic gates; Paper technology; Full adders (FAs); sensitivity to variations; single-electron technology (SET); threshold logic;
Journal_Title :
Nanotechnology, IEEE Transactions on
DOI :
10.1109/TNANO.2005.858609
