A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design

A reconfigurable, highly time-interleaved ADC architecture that substantially decouples comparator requirements from input signal bandwidth and system sampling rate constraints is presented. A highly parallel array of low bandwidth, single slope converters achieves low noise and high linearity with very low input capacitance and signal-independent current consumption. A 128-channel counter ADC, implemented in 0.13 μm CMOS, can be configured in real-time as a 1 GSps 7-bit, 500 MSps 8-bit, or 250 MSps 9-bit converter. Central to this approach is a novel parallel slope ramp-generator based on a rotating figure-of-8 resistor ring. The ADC achieves sub 400 fJ/step in all configurations and a near flat SFDR over the entire input signal frequency range. The figure of merit scales favourably to nanometer CMOS technologies.