Bit-serial multipliers and squarers

Traditional bit-serial multipliers present one or more clock cycles of data-latency. In some situations, it is desirable to obtain the output after only a combinational delay, as in serial adders and subtracters. A serial multiplier and a squarer with no latency cycles are presented here. Both accept unsigned or sign-extended two´s complement numbers and produce an arbitrarily long output. They are fully modular and thus good candidates for introduction in VLSI libraries