Analytical modeling of thermal stresses in plated through via (PTV) structures

Author

Ma, Jin ; Spelt, Jan K.

Author_Institution

Sch. of Mech. & Aerosp. Eng., Oklahoma State Univ., Stillwater, OK, USA

Volume

28

Issue

4

fYear

2005

Firstpage

704

Lastpage

712

Abstract

Plated through via (PTV) structures are widely used in printed circuit boards for interconnect. Due to the mismatch in the coefficient of thermal expansion (CTE) between the PTV and the board material, high thermal stresses can be induced in the PTV during high temperature soldering and normal usage. In particular, PTVs can fail due to cyclic temperature changes which cause thermal fatigue. This paper describes an analytical model of the thermal stresses in PTV structures using variational mechanics. Stress components are compared with those obtained using finite element analysis and with another analytical model.

Keywords

integrated circuit interconnections; printed circuits; thermal expansion; thermal management (packaging); thermal stress cracking; thermal stresses; analytical modeling; coefficient of thermal expansion; cyclic temperature; interconnect; plated through via structures; printed circuit boards; soldering; thermal fatigue; thermal stresses; Analytical models; Bonding; Copper; Fatigue; Finite element methods; Material properties; Printed circuits; Temperature; Thermal expansion; Thermal stresses; Analytical model; plated through via (PTV); reliability; thermal stress; variational mechanics;

fLanguage

English

Journal_Title

Advanced Packaging, IEEE Transactions on

Publisher

ieee

ISSN

1521-3323

Type

jour

DOI

10.1109/TADVP.2005.848394

Filename

1528655