• DocumentCode
    1211730
  • Title

    A Due-Date-Based Algorithm for Lot-Order Assignment in a Semiconductor Wafer Fabrication Facility

  • Author

    Kim, Yeong-Dae ; Bang, June-Young ; An, Kwee-Yeon ; Lim, Seung-Kil

  • Author_Institution
    Dept. of Ind. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon
  • Volume
    21
  • Issue
    2
  • fYear
    2008
  • fDate
    5/1/2008 12:00:00 AM
  • Firstpage
    209
  • Lastpage
    216
  • Abstract
    This paper focuses on a lot-order assignment problem, called the pegging problem, in a semiconductor wafer fabrication facility. Pegging is a process of assigning wafer lots to orders for wafers. We consider two types of pegging strategies: hard pegging strategy, under which the lot-order assignment is not changed once lots are assigned to orders; and soft pegging strategy, under which the lot-order assignment can be changed during the production period. For the soft pegging strategy, we develop three operational policies and three algorithms for the pegging problem of assigning lots to orders with the objective of minimizing total tardiness of the orders. To evaluate performance of the suggested policies and algorithms, we perform simulation experiments using real factory data as well as randomly generated data sets. Results of the simulation tests show that the repegging policies and the algorithms operated under the soft pegging strategy give better results than the hard pegging strategy.
  • Keywords
    semiconductor device manufacture; due-date-based algorithm; hard pegging strategy comparison; lot-order assignment problem; operational policies; pegging problem; production period; randomly generated data sets; real factory data; semiconductor wafer fabrication facility; soft pegging strategy; wafer lots assigning process; Assembly; Companies; Fabrication; Job shop scheduling; Manufacturing processes; Performance evaluation; Production facilities; Semiconductor device manufacture; Semiconductor device testing; Semiconductor materials; Lot-order assignment; scheduling; semiconductor wafer fab;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/TSM.2008.2000261
  • Filename
    4512064