A 300-MHz quadrature direct digital synthesizer/mixer in 0.25-μm CMOS

Author

Torosyan, Arthur ; Fu, Dengwei ; Willson, Alan N., Jr.

Author_Institution

Dept. of Electr. Eng., Univ. of California, Los Angeles, CA, USA

Volume

38

Issue

6

fYear

2003

fDate

6/1/2003 12:00:00 AM

Firstpage

875

Lastpage

887

Abstract

A 300-MHz quadrature direct digital frequency synthesizer/complex mixer (QDDSM) chip is presented. With a 32-bit input frequency control word, the tuning resolution is 0.07 Hz at the operating frequency of 300 MHz. The 12-bit I and Q inputs and 13-bit I and Q outputs offer a spurious-free dynamic range of 90.3 dB. The tuning latency is 13 clock cycles, which corresponds to 43 ns at 300 MHz. The tuning bandwidth (half the operating frequency) is 150 MHz. The IC is realized in 0.25-μm TSMC CMOS technology with 4180 standard library cells and occupies a core area of 0.36 mm². At 300 MHz, the power dissipation is less than 400 mW. A key feature of the design is the creation of conditionally negating multipliers.

Keywords

CMOS digital integrated circuits; built-in self test; circuit tuning; direct digital synthesis; frequency control; high-speed integrated circuits; mixers (circuits); 150 MHz; 300 MHz; 32 bit; 400 mW; BIST; TSMC CMOS technology; angle rotation algorithm; conditionally negating multipliers; quadrature DDS/complex mixer chip; quadrature direct frequency synthesizer; standard library cells; tuning resolution; Bandwidth; CMOS integrated circuits; CMOS technology; Clocks; Delay; Dynamic range; Frequency control; Frequency synthesizers; Libraries; Tuning;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.811877

Filename

1201989