Systolic implementation of FIR decimators and interpolators

An algebraic technique for mapping FIR decimator and interpolator algorithms with integer compression/expansion factors on systolic and semisystolic structures is described. The technique is based on the time-domain representation of the algorithms. The advantages of this technique are that it is suitable for describing multirate algorithms and that the required arithmetic operations are explicitly stated. Applying the algebraic technique, various structures can be obtained in which the number of multipliers is reduced in proportion to the decimation or interpolation factor. Pipelining can be introduced at the input and/or the output. An example is given to illustrate the flexibility and simplicity of the proposed technique