Testing differential split-level CMOS circuits

The paper addresses the problem of testing differential split-level (DSL) CMOS circuits. The behaviour of DSL circuits under single stuck-at, stuck-on and stuck-open faults is analysed. It is shown that most of these faults in DSL circuits cannot be deterministically tested by logic monitoring. However, the presence of any of these faults results in an increase in the steady state power supply current in the circuit when the fault is sensitised. A testing technique based on differential supply current monitoring to detect these faults in DSL integrated circuits is presented