• DocumentCode
    1212740
  • Title

    Enhancement-mode GaAs MESFET technology for low consumption power and low noise applications

  • Author

    Nakajima, Shigeru ; Matsuzaki, Ken-Ichiro ; Otobe, Kenji ; Nishizawa, Hideaki ; Shiga, Nobuo

  • Author_Institution
    Optoelectron. R&D Labs., Sumitomo Electr. Ind. Ltd., Yokohama, Japan
  • Volume
    42
  • Issue
    12
  • fYear
    1994
  • fDate
    12/1/1994 12:00:00 AM
  • Firstpage
    2517
  • Lastpage
    2524
  • Abstract
    Ion-implanted enhancement-mode GaAs MESFET\´s with an advanced Lightly Doped Drain (LDD) structure have been developed for low cost, low consumption power, and low noise applications. The advanced LDD structure, which consists of step graded (n+, n\´, n") source/drain implanted regions and surrounding p-layers located within the n+-layers, is effective to suppress the short channel effects and reduce source/drain parasitic resistance without increasing the parasitic capacitance. A manufacturable self-aligned process based on a dummy gate has also been developed for the fabrication of this structure. The 0.3 μm devices show a noise figure of less than 1 dB with an associated gain of higher than 9 dB at 6 GHz, even at 1 mW operation. Furthermore, standard deviations of noise figure and associated gain are as small as 0.05 dB (at an average of 0.83 dB) and 0.32 dB (at an average of 8.82 dB), respectively, under a 1 mW operation over a 3 inch Φ wafer
  • Keywords
    III-V semiconductors; S-parameters; Schottky gate field effect transistors; equivalent circuits; gallium arsenide; ion implantation; microwave field effect transistors; semiconductor device manufacture; semiconductor device models; semiconductor device noise; semiconductor technology; Φ wafer; 0.3 micron; 1 dB; 1 mW; 6 GHz; 9 dB; GaAs; LDD structure; MESFET technology; dummy gate; enhancement-mode devices; fabrication; ion-implanted devices; lightly doped drain; low consumption power; low noise applications; manufacturable self-aligned process; short channel effects; source/drain parasitic resistance; step graded source/drain implanted regions; Costs; Gallium arsenide; MESFETs; Manufacturing processes; Microwave devices; Mobile communication; Noise figure; Parasitic capacitance; Reproducibility of results; Substrates;
  • fLanguage
    English
  • Journal_Title
    Microwave Theory and Techniques, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9480
  • Type

    jour

  • DOI
    10.1109/22.339791
  • Filename
    339791