Jitter Analysis of Nonautonomous MOS Current-Mode Logic Circuits

In this paper, we analyze the occurrence of jitter due to random and deterministic disturbances in nonautonomous current-mode logic circuits. First, we present an analytical model that explains the transformation of noise into jitter as a linear time-variant process, with its time-domain impulse response function and a frequency-domain system function. The model is then used to analyze jitter in two different circuits, with different sources of noise. In the first example, we use the model to predict jitter due to device noise in a frequency divider, and identify devices that are the main contributors to the jitter. In the second example, we examine jitter of a buffer with deterministic ground noise. Jitter predictions are compared to the results obtained through exhaustive simulation. According to the comparison, the method predicts jitter with an error of up to 3.4%.