Optimum i-layer width of p-i-n diodes for frequency multipliers

p-i-n diodes give their best possible performance as charge-storage diodes in frequency multipliers. The paper deals with the optimum design of the diode parameters to minimise the power loss in the diode. D.C. losses due to recombination of charge carriers and ohmic losses due to the ramp voltage during the turn-off transient are shown to be the most important loss components. Because recombination losses dominate for a small and turn-off losses for a large i-layer width, this design parameter can be optimised. Based upon closed-form solutions for the diode current and the various loss components, the optimum i-layer width is determined and related to the doping concentrations in the highly doped contact layers and to the input frequency of the multiplier.