Investigation of a SiGe HBT during ESD stress in a 0.18-μm SiGe BiCMOS process

Author

Shiao-Shien Chen ; Tung-Yang Chen ; Tien-Hao Tang ; Shao-Chang Huang ; Hsu, T.-L. ; Hua-Chou Tseng ; Jen-Kon Chen ; Chiu-Hsiang Chou

Author_Institution

Device Eng. Dept., United Microelectron. Corp., Taiwan, Taiwan

Volume

24

Issue

3

fYear

2003

fDate

3/1/2003 12:00:00 AM

Firstpage

168

Lastpage

170

Abstract

This paper investigates the electrostatic discharge (ESD) characteristics of the silicon-germanium heterojunction bipolar transistor (SiGe HBT) in a 0.18-μm SiGe BiCMOS process. According to this letter, the open base configuration in the SiGe HBT has lower trigger voltage and higher ESD robustness than a common base configuration. As compared to the gate-grounded NMOS and PMOS in a bulk CMOS process, the SiGe HBT has a higher ESD efficiency from the layout area point of view. Additionally, any trigger biases used to improve the ESD robustness of the SiGe HBT are observed as invalid, and even they can work successfully in bulk CMOS process.

Keywords

BiCMOS integrated circuits; Ge-Si alloys; electrostatic discharge; heterojunction bipolar transistors; protection; semiconductor materials; 0.18 micron; 0.18-/spl mu/m SiGe BiCMOS process; ESD efficiency; ESD robustness; ESD stress; SiGe; SiGe HBT; common base configuration; electrostatic discharge characteristics; layout area; open base configuration; trigger voltage; BiCMOS integrated circuits; CMOS process; Electrostatic discharge; Germanium silicon alloys; Heterojunction bipolar transistors; MOS devices; Robustness; Silicon germanium; Stress; Voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2003.809534

Filename

1202516