Title :
Improved reliability of low-temperature polysilicon TFT by post-annealing gate oxide
Author :
Lee, Seok-Woo ; Kim, Eugene ; Han, Sang-Soo ; Lee, Hye Sun ; Yun, Duk-Chul ; Lim, Kyoung Moon ; Yang, Myoung-Su ; Kim, Chang-Dong
Author_Institution :
LCD R&D Center, LG Philips, Kyongki-Do, South Korea
fDate :
3/1/2003 12:00:00 AM
Abstract :
We have investigated the electrical characteristics of gate oxide films deposited by plasma enhanced chemical vapor deposition (PECVD) with respect to gate oxide integrity (GOI) and its reliability. In the investigation, post-annealed gate oxide was compared with as-deposited oxide. It was shown that the characteristics of GOI strongly depended on the charge trapping characteristics and deep level interface states generation under FN stress, which was remarkably improved by post-annealing after gate oxide deposition. Improved FN stress and hot carrier stress reliability of CMOS devices implemented on the glass substrate are also discussed.
Keywords :
MOS capacitors; annealing; deep levels; elemental semiconductors; hot carriers; interface states; plasma CVD; semiconductor device reliability; silicon; thin film transistors; CMOS devices; Fowler-Nordheim stress; MOS capacitors; PECVD; Si-SiO/sub 2/; charge trapping characteristics; deep level interface states generation; electrical characteristics; gate oxide films; gate oxide integrity; glass substrate; hot carrier stress reliability; low-temperature polysilicon TFT; plasma enhanced chemical vapor deposition; post-annealed gate oxide; post-annealing; reliability; Character generation; Chemical vapor deposition; Electric variables; Glass; Hot carriers; Interface states; Plasma chemistry; Plasma properties; Stress; Thin film transistors;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2003.811398
