What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?

Author

Dambrine, G. ; Raynaud, C. ; Lederer, D. ; Dehan, M. ; Rozeaux, O. ; Vanmackelberg, M. ; Danneville, F. ; Lepilliet, S. ; Raskin, J.P.

Author_Institution

Inst. d´´Electronique et de Microelectronique du Nord, Villeneuve d´´Ascq, France

Volume

24

Issue

3

fYear

2003

fDate

3/1/2003 12:00:00 AM

Firstpage

189

Lastpage

191

Abstract

Parameters limiting the improvement of high frequency characteristics for deep submicron MOSFETs with the downscaling process of the channel gate length are analyzed experimentally and analytically. It is demonstrated that for MOSFETs with optimized source, drain and gate access, the degradation of the maximum oscillation frequency is mainly related to the increase of the parasitic feedback gate-to-drain capacitance and output conductance with the physical channel length reduction. Optimization of these internal parameters is needed to further improve the high frequency performance of ultra deep submicron MOSFETs.

Keywords

MOSFET; capacitance; electric admittance; equivalent circuits; microwave field effect transistors; RF CMOS; channel gate length; channel length reduction; deep-submicron MOSFETs; downscaling process; equivalent circuit; high frequency applications; internal parameter optimization; limiting parameters; maximum oscillation frequency degradation; microwave performance; optimized drain; optimized gate access; optimized source; output conductance; parasitic feedback gate-to-drain capacitance; CMOS technology; Degradation; Equivalent circuits; Frequency; HEMTs; Integrated circuit technology; Length measurement; MODFETs; MOSFETs; Silicon;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2003.809525

Filename

1202523