Pulsed characterisation and nonlinear modelling of four terminal LDMOS for smart power amplifiers

A novel transistor with four terminals (4T) directly based on the silicon LDMOS process is presented. Pulsed I-V and S characterisations are proposed to provide a straightforward method for determining the nonlinear model (NLM) of such a 4T LDMOS. On wafer measurements of devices are done on a specific three-port measurement setup. The agreement between NLM and measured performance is reported.