SWEC speeds VLSI simulation

Author

Lin, Shen ; Kuh, Ernest

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

11

Issue

1

fYear

1995

fDate

1/1/1995 12:00:00 AM

Firstpage

10

Lastpage

15

Abstract

A new simulator called SWEC (StepWise Equivalent Conductance) can efficiently simulate circuits with MOS transistors and passive elements. SWEC adopts four novel techniques: 1) stepwise equivalent conductance implicit integration, 2) piecewise-linear waveform event-driven simulation, 3) recursive convolution formulation based on the Pade approximation, and 4) interconnect partition, to achieve significant speed-ups over existing simulators. The first two timing simulation techniques are briefly reviewed in this article

Keywords

MOS integrated circuits; VLSI; circuit analysis computing; convolution; digital simulation; integrated circuit design; integrated circuit interconnections; piecewise-linear techniques; MOS integrated circuits; Pade approximation; SWEC; VLSI simulation; interconnect partition; passive elements; piecewise-linear waveform event-driven simulation; recursive convolution formulation; stepwise equivalent conductance; timing simulation techniques; Circuit simulation; Clocks; Computational modeling; Coupling circuits; Delay estimation; Discrete event simulation; SPICE; Switching circuits; Timing; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Devices Magazine, IEEE

Publisher

ieee

ISSN

8755-3996

Type

jour

DOI

10.1109/101.340306

Filename

340306